New Xena Networks 5-speed dual-media test module


The M1QSFP28SFP28 is a 5-speed (10GE, 25GE, 40GE, 50GE, 100GE) dual-media test module.

New 5-speed dual-media test module

The new Xena Networks 5-speed dual-media test module M1QSFP28SFP28 is a versatile test solution offering five different Ethernet network speeds: 10GE, 25GE, 40GE, 50GE and 100GE. This unique test module lets users dynamically choose between two different physical transceiver cages and form factors. The first is a single QSFP28/QSFP+ transceiver cage, and the second is two SFP28/SFP+ transceiver cages.

When using the QSFP28/QSFP+ cage, the user can dynamically select between the following modes of operation: 4x10GE / 1x40GE / 4x25GE / 2x50GE / 1x100GE test ports, and when using the dual SFP28 cages: 2 x 10GE / 2x25GE.

The unique combination of five different Ethernet network speeds and multiple physical optical transceiver form factors, makes the M1QSFP28SFP28 a versatile solution for performance and functional testing of network infrastructure and Ethernet equipment such as taps, switches, routers, NICs, packet-brokers, and backhaul platforms.

M1QSFP28SFP28 is the new Xena Networks 5-speed dual-media test module

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One module – multiple options

The M1QSFP28SFP28 lets you dynamically choose between 2 transceiver cages. This determines which speeds and number of ports you can use. Once the physical transceiver cage is in use, you can use XenaManager-2G (Xena’s free traffic generation and analysis software) to specify which Ethernet speeds to use.

Unique Eye Diagram

The new Xena Networks 5-speed dual-media test module M1QSFP28SFP28 includes a unique feature for analyzing signal quality called the “eye diagram”. When using the QSFP28 ports, an additional panel called “Advanced PHY Features“ will appear in the main Resource Properties tab of XenaManager-2G. This panel controls and monitors the four receive SerDes associated with the 4x10G or 4x25G link at the physical level. It also creates bit-error-rate (BER) eye diagrams, estimates the link BER from the vertical and horizontal BER bathtub curves and controls the PHY tuning in the transmit and the receive directions.

How it works
The BER eye-diagram provides a direct visual representation of the signal quality after RX equalization. The eye-diagram is formed by changing the time dimension (sampling delay) and the amplitude dimension (0/1 threshold) of the sampling point of the PHY step-by-step. For each sampling point (x,y), 1 million bits are measured, the number of bit-errors are counted and a simple division gives the BER. The result is the BER eye-diagram (see below).

The color map shows the measured bit-error rate for each point going from 1 million (maximum red) to zero (black). The color scale is logarithmic. Higher resolutions give a clearer diagram and higher values of X and Y will also give a higher precision in the vertical and horizontal bathtub curve estimations, respectively.

What it shows
The eye-data table provides an estimate of several parameters of the eye, including width, height and jitter. Future releases will also include link BER estimates based on the horizontal and vertical bathtub curves.

See here for more information on the “eye” diagram feature.


Interface categoryCXP: 100G, 40G and 10G Ethernet
CFP4/QSFP28 : 100G Ethernet
QSFP+ : 40G Ethernet
Number of test portsCXP: 1 x 100G / 2 x 40G / 8 x 10G
CFP4/QSFP28: 1 x 100G
QSFP+ : 1 x 40G
Interface optionsCXP: 100GBASE-SR10, 40GBASE-iSR4 / 8 x 10GBASE-iSR(4)
CFP4: 100GBASE-SR4 , 100GBASE-LR4, 100GBASE-CR4(3)
Forward Error Correction (FEC)RS-FEC (Reed Solomon) FEC, IEEE 802.3 Clause 91
Number of transceiver module cages1 x CXP, 1 x CFP4, 1 x QSFP28/QSFP+ (only one cage can be used at a time)
Port statistics (2)Link state, FCS errors, pause frames, ARP/PING, error injections, training packet
All traffic: RX and TX Mbit/s, packets/s, packets, bytes
Traffic w/o test payload: RX and TX Mbit/s, packets/s, packets, bytes
Adjustable Inter Frame Gap (IFG)Configurable from 16 to 56 bytes, default is 20B (12B IFG + 8B preamble)
Transmit line rate adjustmentAbility to adjust the effective line rate by forcing idle gaps equivalent to -1000 ppm (increments of 10 ppm)
Transmit line clock adjustmentFrom -400 to 400 ppm in steps of 0.001 ppm (shared across all ports)
ARP/PINGSupported (configurable IP and MAC address per port)
Field upgradeableSystem is fully field upgradeable to product releases (FPGA images and Software)
Histogram statistics (2)Two real-time histograms per port. Each histogram can measure one of RX/TX packet length, IFG, jitter, or latency distribution for all traffic, a specific stream, or a filter.
Tx disableEnable/disable of optical laser or copper link
IGMPv2 multicast join/leave)IGMPv2 continuous multicast join, with configurable repeat interval
Loopback modes• L1RX2TX – RX-to-TX, transmit byte-by-byte copy of the incoming packet
• L2RX2TX – RX-to-TX, swap source and destination MAC addresses (1)
• L3RX2TX – RX-to-TX, swap source and destination MAC addresses and IP addresses (1)
• TXON2RX – TX-to-RX, packet is also transmitted from the port
• TXOFF2RX – TX-to-RX, port’s transmitter is idle
• Port-to-port – Inline loop mode where all traffic is looped 100% transparent at L1
Oscillator characteristics• Initial Accuracy is 3 ppm
• Frequency drift over 1st year: +/- 3 ppm (over 15 years: +/- 15 ppm)
• Temperature Stability: +/- 20 ppm (Total Stability is +/- 35 ppm)
Payload Test patternPRBS 2^31
Error InjectionManual single shot bit-errors or bursts, automatic continuous error injection
Frame size and headerFixed size from 56 to 9200 bytes, any layer 2/3/4 frame header
AlarmsPattern loss, bit-error rate threshold
Error analysisbit-errors: seconds, count, rate
mismatch ‘0’ / ‘1’: seconds, count, rate
logging and analysis of bit-error event timing
PCS virtual lane configurationUser defined skew insertion per Tx virtual lane, and user defined virtual lane to SerDes mapping for testing of the Rx PCS virtual lane re-order function.
PCS virtual lane statisticsRelative virtual lane skew measurement (up to 2048 bits), sync header and PCS lane marker error counters, indicators for loss of sync header and lane marker, BIP8 errors
Number of transmit streams per port256 (wire-speed) continuous.
Test payload insertion per streamWire-speed packet generation with timestamps, sequence numbers, and data integrity signature optionally inserted into each packet.
Stream statistics (2)TX Mbit/s, packets/s, packets, bytes, FCS error, Pause
Bandwidth profilesBurst size and density can be specified. Uniform and bursty bandwidth profile streams can be interleaved
Field modifiers16-bit header field modifiers with inc, dec, or random mode. Each modifier has configurable bit-mask, repetition, min, max, and step parameters. 6 modifiers per stream.
Packet length controlsFixed, random, butterfly, and incrementing packet length distributions. Packet length from 56 to 9200 bytes
Packet payloadsRepeated user specified 1 to 18B pattern, an 8-bit incrementing pattern
Error generationUndersize length (56B min) and oversize length (9200 max.) packet lengths, injection of sequence, misorder, payload integrity, and FCS errors
TX packet header support and RX autodecodesEthernet, Ethernet II, VLAN, ARP, IPv4, IPv6, UDP, TCP, LLC, SNAP, GTP, ICMP, RTP, RTCP, STP, MPLS, PBB, or fully specified by user
Packet scheduling modes• Normal (stream interleaved mode). Standard scheduling mode, precise rates, minor variation in packet inter-frame gap.
• Strict Uniform. New scheduling mode, with 100% uniform packet inter-frame gap, minor deviation from configured rates
• Sequential packet scheduling (sequential stream scheduling). Streams are scheduled continuously in sequential order, with configurable number of packets per stream
Number of traceable Rx streams per port2016 (wire-speed)
Automatic detection of test payload for received packetsReal-time reporting of statistics and latency, loss, payload integrity, sequence error, and misorder error checking
Jitter measurementJitter (Packet Delay Variation) measurements compliant to MEF10 standard with 8 ns accuracy. Jitter can be measured on up to 32 streams.
Stream statistics 2)• RX Mbit/s, packets/s, packets, bytes.
• Loss, payload integrity errors, sequence errors, misorder errors
• Min latency, max latency, average latency
• Min jitter, max jitter, average jitter
Latency measurements accuracy±64 ns (opto/elec).
Latency measurement resolution 8 ns (Latency measurements can calibrate and remove latency from transceiver modules)
Number of filters:• 4 x 64-bit user-definable match-term patterns with mask, and offset
• 4 x frame length comparator terms (longer, shorter)
• 4 x user-defined filters expressed from AND/OR’ing of the match and length terms.
Filter statistics (2)Per filter: RX Mbit/s, packets/s, packets, bytes.
Capture criteriaAll traffic, stream, FCS errors, filter match, or traffic without test payloads
Capture start/stop triggersCapture start and stop trigger: none, FCS error, filter match
Capture limit per packet16 – 12288 bytes
Wire-speed capture buffer per port256 kB for 100G
128 kB for 40G
Low speed capture buffer per port (10Mbit/sec)4096 packets (any size)
Transmit Equalization Controls- Tx Transmit Equalization Controls Pre-emphasis
- Tx Attenuation
- Tx Post-emphasis Signal Integrity Analysis Graphical “eye” diagram
- Rx Optional Auto-Tune of PHY 25Gbps Rx SerDes
Signal Integrity Analysis- Graphical “eye” diagram
- Horizontal bathtub curve estimation
- Vertical bathtub curve estimation
- Bit Error Rate (BER) estimation
100G Clause 91 Reed-Solomon
Forward Error Correction (CL91 RS-FEC)
Selectable Tx line rateTx line rate can be referenced to either local clock oscillator (adjustable in steps of 1 ppm), SMA input, or from the Rx line rate for Synchronous Ethernet applications. The Tx line rate complies with SONET/SDH/SyncE with respect to wander and jitter.
Jitter attenuationSelectable loop bandwidth for jitter attenuation: 114 Hz, 229 Hz, 460 Hz, 1864 Hz, or 7834 Hz loop bandwidth
SMA input- 10.0 MHz, or 2.048 MHz Tx line rate reference clock SMA input
- (Drift/wander is passed from SMA input to Tx line rate)
- 250mV-2.5V, loaded 50 ohm, square wave format
(1) Only at 10G

(2) Counter size: 64 bits

(3) With customized Xena cable, IEEE 802.3 Clause 73, Auto-negotiation, and IEEE 802.3 Clause 72, Link training are possible.

(4) iSR4 - where “i” represents interoperability between the QSFP+ transceiver with any 10GBASE-SR compliant modules.


  • Multi-speed flexibility 10GE, 25GE, 40GE, 50GE and 100GE
  • Double media flexibility
  • Great price/performance
  • Ease of use
  • Unique “eye” diagram for signal analysis
  • Free software
  • Free 12-month hardware warranty
  • 36 months free software updates
  • Free tech support for product lifetime

Includes this free software:

XenaManager-2G software xena-scripting-270 xena-2544-270 xena-2889-270 xena-1564-270 xena-3918-270

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