The M1CFP100 is a unique 100/40G/10Gbps test module

M1CFP100

The M1CFP100 is a unique 100G/40G/10Gbps test module

Unique 100/40G/10Gbps test module

Xena Networks’ M1CFP100 is a unique 100/40/10G test module for the XenaCompact and XenaBay chassis.

Via a simple software setting, it can be used as a single 100G test port, two 40G test ports or eight 10G test ports. This flexibility and price/ performance makes it idea for BERT, load-stress, and functional testing of Ethernet equipment and network infrastructure.

Xena’s M1CFP100 provides one 100Gbps, two 40Gbps test ports or eight 10Gbps test ports.

The first of its kind in the world, this 3-speed capability is ideal for lab testing, pre-staging, field trials and early deployments, and applications where wire-speed testing, portability, and ease of use are required.

Changing between the three speeds is extremely simple – just select the speed you need in XenaManager-2G, the free GUI provided for managing Xena’s chassis and test modules.

This test module is available for both the XenaCompact chassis and as a 2-slot test module for the 12-slot XenaBay chassis for larger port-counts.

PORT LEVEL FEATURES
Interface category100, 40 and 10 Gigabit Ethernet
Number of test ports1 x 100G / 2 x 40G / 8 x 10G (software configurable)
Interface options1 x 100GBASE-LR4
1 x 40GBASE-LR4
1 x 100GBASE-SR10(3)
2 x 40GBASE-SR4(3)
8 x 10GBASE-SR(3)
Number of transceiver module cages1 x CFP
Port statistics(2)Link state, FCS errors, pause frames, ARP/PING, error injections, training packet
All traffic: RX and TX Mbit/s, packets/s, packets, bytes
Traffic w/o test payload: RX and TX Mbit/s, packets/s, packets, bytes
Adjustable Inter Frame Gap (IFG)Configurable from 16 to 56 bytes, default is 20B (12B IFG + 8B preamble)
Transmit line rate adjustmentAbility to adjust the effective line rate by forcing idle gaps equivalent to -1000 ppm (increments of 10 ppm)
Transmit line clock adjustmentFrom -400 to 400 ppm in steps of 0.001 ppm (shared across all ports)
ARP/PINGSupported (configurable IP and MAC address per port)
Field upgradeableSystem is fully field upgradeable to product releases (FPGA images and Software)
Histogram
statistics(2)
Two real-time histograms per port. Each histogram can measure one of RX/TX packet length, IFG, jitter, or latency distribution for all traffic, a specific stream, or a filter.
Tx disableEnable/disable of optical laser or copper link
IGMPv2 multicast join/leave)IGMPv2 continuous multicast join, with configurable repeat interval
Loopback modes• L1RX2TX – RX-to-TX, transmit byte-by-byte copy of the incoming packet(1)
• L2RX2TX – RX-to-TX, swap source and destination MAC addresses(1)
• L3RX2TX – RX-to-TX, swap source and destination MAC addresses and IP addresses(1)
• TXON2RX – TX-to-RX, packet is also transmitted from the port
• TXOFF2RX – TX-to-RX, port’s transmitter is idle
• Port-to-port – Inline loop mode where all traffic is looped 100% transparent at L1(1)
Oscillator characteristics• Initial Accuracy is 3 ppm
• Frequency drift over 1st year: +/- 3 ppm (over 15 years: +/- 15 ppm)
• Temperature Stability: +/- 20 ppm (Total Stability is +/- 35 ppm)
100/40 GE PRBS & PCS LAYERS
Payload Test patternPRBS 2^31
Error InjectionManual single shot bit-errors or bursts, automatic continuous error injection
Frame size and headerFixed size from 56 to 9200 bytes, any layer 2/3/4 frame header
AlarmsPattern loss, bit-error rate threshold
Error analysisbit-errors: seconds, count, rate
mismatch ‘0’ / ‘1’: seconds, count, rate
logging and analysis of bit-error event timing
PCS virtual lane configurationUser defined skew insertion per Tx virtual lane, and user defined virtual lane to SerDes mapping for testing of the Rx PCS virtual lane re-order function.
PCS virtual lane statisticsRelative virtual lane skew measurement (up to 2048 bits), sync header and PCS lane marker error counters, indicators for loss of sync header and lane marker, BIP8 errors
PCB Tx line clock adjustment (FCO)Ability to adjust the parts per million (ppm) Tx frequency over a range of -400 to +400 ppm
TRANSMIT ENGINE
Number of transmit streams per port64 (wire-speed) continuous.
Test payload insertion per streamWire-speed packet generation with timestamps, sequence numbers, and data integrity signature optionally inserted into each packet.
Stream statistics(2)TX Mbit/s, packets/s, packets, bytes, FCS error, Pause
Bandwidth profilesBurst size and density can be specified. Uniform and bursty bandwidth profile streams can be interleaved
Field modifiers16-bit header field modifiers with inc, dec, or random mode. Each modifier has configurable bit-mask, repetition, min, max, and step parameters. 2 modifiers per stream.
Packet length controlsFixed, random, butterfly, and incrementing packet length distributions. Packet length from 56 to 9200 bytes
Packet payloadsRepeated user specified 1 to 18B pattern, an 8-bit incrementing pattern
Error generationUndersize length (56B min) and oversize length (16384 max.) packet lengths, injection of sequence, misorder, payload integrity, and FCS errors
TX packet header support and RX autodecodesEthernet, Ethernet II, VLAN, ARP, IPv4, IPv6, UDP, TCP, LLC, SNAP, GTP, ICMP, RTP, RTCP, STP, MPLS, PBB, or fully specified by user
Packet scheduling modes- Normal (stream interleaved mode). Standard scheduling mode, precise rates, minor variation in packet inter-frame gap.
- Strict Uniform. New scheduling mode, with 100% uniform packet inter-frame gap, minor deviation from configured rates
- Sequential packet scheduling (sequential stream scheduling). Streams are scheduled continuously in sequential order, with configurable number of packets per stream
RECEIVE ENGINE
Number of traceable Rx streams per port480 (wire-speed)
Automatic detection of test payload for received packetsReal-time reporting of statistics and latency, loss, payload integrity, sequence error, and misorder error checking
Jitter measurementJitter (Packet Delay Variation) measurements compliant to MEF10 standard with 8 ns accuracy. Jitter can be measured on up to 32 streams.
Stream statistics(2)- RX Mbit/s, packets/s, packets, bytes.
- Loss, payload integrity errors, sequence errors, misorder errors
- Min latency, max latency, average latency
- Min jitter, max jitter, average jitter
Latency measurements accuracy±32 ns (opto/elec).
Latency measurement resolution 8 ns (Latency measurements can calibrate and remove latency from transceiver modules)
Number of filters:- 4 x 64-bit user-definable match-term patterns with mask, and offset
- 4 x frame length comparator terms (longer, shorter)
- 4 x user-defined filters expressed from AND/OR’ing of the match and length terms.
Filter statistics 2)Per filter: RX Mbit/s, packets/s, packets, bytes.
CAPTURE
Capture criteriaAll traffic, stream, FCS errors, filter match, or traffic without test payloads
Capture start/stop triggersCapture start and stop trigger: none, FCS error, filter match
Capture limit per packet16 – 9200 bytes
Wire-speed capture buffer per port256 kB
Low speed capture buffer per port (10Mbit/sec)4096 packets (any size)

(1) Only at 10G

(2) Counter size: 64 bits

(3) Requires Reflex Photonics CFP 100GBASE-SR10 Parallel Optical Transceiver

 

TOP FEATURES

  • 1 x 100G or 2 x 40G or 8 x 10G ports
  • Price/performance
  • Testing flexibility
  • Ease of use
  • Free software
  • Free 12-month hardware warranty
  • 36 months free software updates
  • Free tech support for product lifetime

Includes this free software:

XenaManager-2G software xena-scripting-270 xena-2544-270 xena-2889-270 xena-1564-270 xena-3918-270

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