Evaluating 1588v2 Performance

IEEE 1588v2 is the preferred protocol for transport frequency and phase synchronization over Ethernet, which is required for 3G and 4G mobile networks.

Ethernet devices & traffic add Packet Delay Variation (PDV), which can affect 1588v2 clock recovery. If you only rely on an Ordinary (Slave) Clock, PDV can mean the recovered frequency and phase do not meet accuracy specs. Adding Boundary clocks (BCs) and Transparent clocks (TCs) to the network helps Slave clocks recover frequency and phase more accurately. BCs effectively reduce the PDV, while TCs report the delays to the Slave Clock.

This Application Note describes a test plan for evaluating the performance of both Boundary clocks (BCs) and Transparent clocks (TCs) based on solutions from Calnex and Xena Networks.