Live WEBINAR – 8 December

112Gbps SerDes Masterclass

112Gbps SerDes Masterclass

On 8 December, join us for a masterclass in implementing 112Gbps SerDes.

This is a “must-attend” event for any engineer preparing to upgrade from 56Gbps PAM4 to Ethernet’s newest high-speed, 112Gbps SerDes.

The webinar will feature presentations from four leading experts in high-speed Ethernet, followed by an open panel Q&A where you are invited to submit your questions in advance.


112G Link Design Best Practices – An End-to-End Approach

AMD XILINX

Presenter: Martin Gilpatric (Sr. Technical Marketing Manager – Transceiver Technology) & Jun Wang (Sr. Technical Marketing Manager – Transceiver & SI)

Incorporating 112G links into high-performance products brings both opportunity and new engineering challenges. Martin Gilpatric will outline top considerations when designing systems for 112G – from protocol selection to transceiver configuration, to channel design, simulation, and testing


Navigating Physical Layer Challenges of 112G SerDes Development

MultiLane

Presenter: Hani Daou (Senior Applications Engineer)

SI design and thermal management are two of the most significant challenges of physical layer 112G/lane SerDes. Hani Daou will address both these issues and highlight how MultiLane can support chip and system developers from a very early stage.


112G Link Training Testing – Protocol and Performance

Xena Networks 

Presenter: Claus Hoyer (VP Technology & Architecture)

Moving from 56G to 112G SerDes speed has increased the criticality of a robust AN/LT implementation for successful Ethernet link establishment. Claus Hoyer will outline key end-point AN/LT protocol testing parameters and present strategies for achieving superior Signal Integrity.


Making AN/LT reliable at 112Gbps speeds

Teledyne LeCroy

Presenter: Craig Foster (Product Line Manager)

Each new speed increase brings additional challenges for AN/LT interoperability. Craig Foster will share common issues encountered in the AN/LT link bring up as well as some processes to help improve reliability.


This live webinar will take place on Thursday, 8 December:

10.30 a.m. – 12 noon PST
1.30 p.m. – 3 p.m. EST
7.30 p.m. – 9 p.m. CET

Note that if you cannot attend, we will share a recording of the webinar with all registrants.

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