112Gbps SerDes Masterclass
On 8 December, Xena Networks joined forces with AMD Xilinx, MultiLane and Teledyne LeCroy to provide a masterclass in implementing 112Gbps SerDes.
Any engineer preparing to upgrade from 56Gbps to 112Gbps SerDes will find a wealth of valuable information in these four presentations.
Complete the form opposite to watch the recording.
112G Link Design Best Practices – An End-to-End Approach
Presenter: Martin Gilpatric (Sr. Technical Marketing Manager – Transceiver Technology) & Jun Wang (Sr. Technical Marketing Manager – Transceiver & SI)
Incorporating 112G links into high-performance products brings both opportunity and new engineering challenges. Martin Gilpatric will outline top considerations when designing systems for 112G – from protocol selection to transceiver configuration, to channel design, simulation, and testing
Navigating Physical Layer Challenges of 112G SerDes Development
Presenter: Hani Daou (Senior Applications Engineer)
SI design and thermal management are two of the most significant challenges of physical layer 112G/lane SerDes. Hani Daou will address both these issues and highlight how MultiLane can support chip and system developers from a very early stage.
112G Link Training Testing – Protocol and Performance
Presenter: Claus Hoyer (VP Technology & Architecture)
Moving from 56G to 112G SerDes speed has increased the criticality of a robust AN/LT implementation for successful Ethernet link establishment. Claus Hoyer will outline key end-point AN/LT protocol testing parameters and present strategies for achieving superior Signal Integrity.
Making AN/LT reliable at 112Gbps speeds
Presenter: Craig Foster (Product Line Manager)
Each new speed increase brings additional challenges for AN/LT interoperability. Craig Foster will share common issues encountered in the AN/LT link bring up as well as some processes to help improve reliability.