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Interface category
OSFP 800G, 400G, 200G, 100G Ethernet
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Total number of test ports (software configurable)
1x800G, 2x400G, 4x200G and 8x100G Ethernet
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Interface options
OSFP cage:
1 x 800GE or PAM4 Consortium**
2 x 400GE or PAM4 802.3ck
4 x 200GE or PAM4 802.3ck
8 x 100GE or PAM4 802.3ck
Power capacity of OSFP cage: 15W (ValkyrieBay) / 25W (ValkyrieCompact).
** As defined by Ethernet Technology Consortium
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Auto Negotiation and Link Training
IEEE 802.3 Clause 73, Consortium 800G specification, Auto-negotiation
IEEE 802.3 Clause 72, Link training
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Forward Error Correction (FEC)
RS-FEC (Reed Solomon) (544,514,t=15), IEEE 802.3 Clause 119, Clause 134
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Number of transceiver module cages
1 x OSFP
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Port statistics
Link state, FCS errors, RX and TX Mbit/s, packets/s, packets, bytes
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Adjustable Inter Frame Gap (IFG)
Configurable from 16 to 56 bytes, default is 20B (12B IFG + 8B preamble)
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Transmit line rate adjustment
Ability to adjust the effective line rate by forcing idle gaps equivalent to -1000 ppm (increments of 10 ppm)
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Transmit line rate adjustment
Ability to adjust the effective line rate by forcing idle gaps equivalent to -1000 ppm (increments of 10 ppm)
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Transmit line clock adjustment
From -400 to 400 ppm in steps of 0.001 ppm (shared across all ports)
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Field upgradeable
System is fully field upgradeable to product releases (FPGA images and software)
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Tx disable
Enable/disable of optical laser or copper link
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Loopback modes
- L1RX2TX – RX-to-TX, transmit byte-by-byte copy of the incoming packet
- TXON2RX – TX-to-RX, packet is also transmitted from the port
- TXOFF2RX – TX-to-RX, port’s transmitter is idle
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Oscillator characteristics
- Initial Accuracy is 3 ppm
- Frequency drift over 1st year: +/- 3 ppm (over 15 years: +/- 15 ppm)
- Temperature Stability: +/- 20 ppm (Total Stability is +/- 35 ppm)
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Payload Test pattern
PRBS-31Q
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Alarms
PRBS pattern loss, link sync loss
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Error analysis
Bit-errors: seconds, count, rate
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PCS virtual lane configuration
User-defined skew insertion per Tx virtual lane, and user defined virtual lane to SerDes mapping for testing of the Rx PCS virtual lane re-order function
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PCS virtual lane statistics
Relative virtual lane skew measurements (up to 2048 bits)
Corrected Bit error, PreFEC BER
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FEC Total statistics
Total corrected FEC symbols, Total uncorrected FEC symbols, Estimated Pre-FEC BER, Estimated Post-FEC BER, Pre-FEC Error Distribution Graph
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Link Flap
Single short or repeatable link down events with ms precision
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Error Injection (PMA Layer)
Repeatable error inject periods at PMA layer with ms precision
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Payload Test pattern
PRBS-31Q
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Alarms
PRBS pattern loss, link sync loss
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Error analysis
Bit-errors: seconds, count, rate
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PCS virtual lane configuration
User-defined skew insertion per Tx virtual lane, and user defined virtual lane to SerDes mapping for testing of the Rx PCS virtual lane re-order function
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PCS virtual lane statistics
Relative virtual lane skew measurements (up to 2048 bits)
Corrected Bit error, PreFEC BER
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FEC Total statistics
Total corrected FEC symbols, Total uncorrected FEC symbols, Estimated Pre-FEC BER, Estimated Post-FEC BER, Pre-FEC Error Distribution Graph
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Link Flap
Single short or repeatable link down events with ms precision
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Error Injection (PMA Layer)
Repeatable error inject periods at PMA layer with ms precision
DataSheet
