4-speed 800G (112Gbps SerDes) dual-media test module


The Freya-800G-1S-1P test module supports four Ethernet network speeds –
800GE, 400GE, 200GE and 100GE using 112G SerDes (PAM4 112G) with the ability to drive both optical transceivers and DACs.

This flexibility is provided via a physical transceiver cage supporting QSFP-DD800 compatible transceivers. The QSFP-DD800 cage supports the following ports and speeds: 1x800GE, 2x400GE, 4x200GE and 8x100GE.

The newest addition to Xena’s Xena product line, Freya-800G-1S-1P is a highly versatile solution for performance and functional testing of network infrastructure and Ethernet equipment including switches, routers, NICs, TAPs, packet-brokers, and backhaul platforms.

In addition, the comprehensive PCS and PMA layer test capabilities facilitates thorough transceiver and PHY testing. This includes the advanced signal integrity view, which provides visual information on the quality of the received signal.


Top Features

  • 4-speeds: 800GE, 400GE, 200GE, & 100GE
  • QSFP-DD800 cage
  • Supports 112G SerDes (PAM4 112G)
  • Test with optics and DACs
  • Comprehensive PCS & PMA layer test capabilities
  • Advanced signal integrity view
  • Price/performance
  • Ease of use

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  1. Interface category

    QSFP-DD800 : 800G, 400G, 200G, 100G Ethernet

  2. Total number of test ports (software configurable)

    1x800G, 2x400G, 4x200G and 8x100G Ethernet

  3. Interface options

    QSFP-DD800 cage:

    1 x 800GE or           PAM4       Consortium**
    2 x 400GE or           PAM4           802.3ck
    4 x 200GE or           PAM4           802.3ck
    8 x 100GE or           PAM4           802.3ck
    2 x 100GE or           PAM4           802.3ck
    1 x 100GE              PAM4           802.3ck

    Power capacity per QSFP-DD800 cage: 15W (XenaBay) / 25W (XenaCompact)

    ** As defined by Ethernet Technology Consortium

  4. Forward Error Correction (FEC)

    RS-FEC (Reed Solomon) (544,514,t=15), IEEE 802.3 Clause 119, Clause 134

  5. Number of transceiver module cages

    1 x QSFP-DD800

  6. Port statistics*

    Link state, FCS errors, pause frames, ARP/PING, error injections, training packet
    All traffic: RX and TX Mbit/s, packets/s, packets, bytes
    Traffic w/o test payload: RX and TX Mbit/s, packets/s, packets, bytes

  7. Adjustable Inter Frame Gap (IFG)

    Configurable from 16 to 56 bytes, default is 20B (12B IFG + 8B preamble)

  8. Transmit line rate adjustment

    Ability to adjust the effective line rate by forcing idle gaps equivalent to -1000 ppm (increments of 10 ppm)

  9. Transmit line clock adjustment

    From -400 to 400 ppm in steps of 1 ppm (shared across all ports)

  10. ARP/PING*

    Supported (configurable IP and MAC address per port)

  11. Field upgradeable

    System is fully field upgradeable to product releases (FPGA images and software)

  12. Tx disable

    Enable/disable of optical laser or copper link

  13. IGMPv2 multicast join/leave*

    IGMPv2 continuous multicast join, with configurable repeat interval

  14. Histogram statistics*

    Two real-time histograms per port. Each histogram can measure one of RX/TX packet length, IFG, or Latency distribution for all traffic, a specific stream, or a filter

  15. Loopback modes

    • L1RX2TX – RX-to-TX, transmit byte-by-byte copy of the incoming packet
    • TXON2RX – TX-to-RX, packet is also transmitted from the port
    • TXOFF2RX – TX-to-RX, port’s transmitter is idle
  16. Oscillator characteristics

    • Initial Accuracy is 3 ppm
    • Frequency drift over 1st year: +/- 3 ppm (over 15 years: +/- 15 ppm)
    • Temperature Stability: +/- 20 ppm (Total Stability is +/- 35 ppm)
  17. * 2 x 100GE mode only


  1. Payload Test pattern


  2. Alarms

    PRBS pattern loss, link sync loss

  3. Error analysis

    Bit-errors: seconds, count, rate

  4. PCS virtual lane configuration

    User-defined skew insertion per Tx virtual lane, and user defined virtual lane to SerDes mapping for testing of the Rx PCS virtual lane re-order function

  5. PCS virtual lane statistics

    Relative virtual lane skew measurements (up to 2048 bits) Corrected Bit error, PreFEC BER

  6. FEC Total statistics

    Total corrected FEC symbols, Total uncorrected FEC symbols, Estimated Pre-FEC BER, Estimated Post-FEC BER, Pre-FEC Error Distribution Graph

  7. Link Flap

    Single short or repeatable link down events with ms precision

  8. Error Injection (PMA Layer)

    Repeatable error inject periods at PMA layer with ms precision


  1. Traffic generation

    Ethernet frames with FCS
    Traffic load: up to 100%
    Configurable Frame Size distribution
    Transmit and Receive Statistics


  1. Equalization Controls

    Tx Transmit Equalization Controls

    • Pre-emphasis
    • Attenuation
    • Post-emphasis

    Optional Auto-Tune of Rx equalizer/CTLE

  2. Signal Integrity Analysis

    • FEC error correction chart
    • Advanced signal integrity view


  1. Number of transmit streams per port

    256 (wire-speed).
    Each stream can generate millions of traffic flows using field modifiers

  2. Test payload insertion per stream

    Wire-speed packet generation with timestamps, sequence numbers, and data integrity signature optionally inserted into each packet.

  3. Stream statistics

    TX Mbit/s, packets/s, packets, bytes, FCS error

  4. Bandwidth profiles

    Burst size and density can be specified. Uniform and bursty bandwidth profile streams can be interleaved

  5. Field modifiers

    16-bit or 32-bit header field modifiers with inc, dec, or random mode. Each modifier has configurable bit- mask, repetition, min, max, and step parameters. Eight 16-bit modifiers per stream or four 32-bit modifiers per stream

  6. Packet length controls

    Fixed, random, butterfly, and incrementing packet length distributions from 56 to 12288 bytes

  7. Packet payloads (basic)

    Repeated user specified 1 to 18B pattern, an 8-bit incrementing pattern

  8. Extended payload

    Fixed full custom payloads can be generated for each stream with payload sizes up to 12288 bytes

  9. Error generation

    Undersize length (56 bytes min) and oversize length (12288 bytes max.) packet lengths, injection of sequence, misorder, payload integrity, and FCS errors

  10. TX packet header support and RX autodecodes

    Ethernet, Ethernet II, VLAN, ARP, IPv4, IPv6, UDP, TCP, LLC, SNAP, GTP, ICMP, RTP, RTCP, STP, MPLS, PBB, or fully specified by user

  11. Packet scheduling modes

    • Normal (stream interleaved mode) – standard scheduling mode, precise rates, minor variation in packet inter-frame gap.
    • Strict Uniform – new scheduling mode, with 100% uniform packet inter-frame gap, minor deviation from configured rates.
    • Sequential packet scheduling (sequential stream scheduling). Streams are scheduled continuously in sequential order, with configurable number of packets per stream.
    • Burst. Packets in a stream are organized in bursts. Bursts from active streams form a burst group. The user specifies time from start of one burst group till start of next burst group.

RECEIVE ENGINE (2 x 100GE mode)

  1. Number of traceable Rx streams per port

    2016 (wire-speed)

  2. Automatic detection of test payload for received packets

    Real-time reporting of statistics and latency, loss, payload integrity, sequence error, and misorder error checking

  3. Jitter measurement

    Jitter (Packet Delay Variation) measurements compliant to MEF10 standard with 8 ns accuracy
    Jitter can be measured on up to 32 streams

  4. Stream statistics

    • RX Mbit/s, packets/s, packets, bytes.
    • Loss, payload integrity errors, sequence errors, misorder errors
    • Min latency, max latency, average latency
    • Min jitter, max jitter, average jitter
  5. Latency measurements accuracy

    ±32 ns

  6. Latency measurement resolution

    8 ns (Latency measurements can calibrate and remove latency from transceiver modules)

  7. Number of filters:

    • 6 x 64-bit user-definable match-term patterns with mask, and offset
    • 6 x frame length comparator terms (longer, shorter)
    • 6 x user-defined filters expressed from AND/OR’ing of the match and length terms
  8. Filter statistics

    Per filter: RX Mbit/s, packets/s, packets, bytes.

CAPTURE (2 x 100GE mode)

  1. Capture criteria

    All traffic, stream, FCS errors, filter match, or traffic without test payloads

  2. Capture limit per packet

    16 – 12288 bytes

  3. Wire-speed capture buffer per port

    96 kB for 100GE

  4. Low speed capture buffer per port (10Mbit/s speed)

    4096 packets (any size)


  1. Max. Power


  2. Weight

    1.32 lbs (0.6 kg)

  3. Environmental

    Operating Temperature: 10 to 35º C
    Storage Temperature: -40 to 70º C
    Humidity: 8% to 90% non-condensing

  4. Regulatory

    FCC (US), CE (Europe)

  5. Notes

    This module is only supported by the Val-C12-2400 chassis

    This module requires two slots in the Val-C12-2400 chassis

Includes this free software

Technical Documentation

Relevant Products

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Masterclass Webinar #3: Succeeding with 112G SerDes