Part of the Valkyrie stateless test platform, the Loki-100G-3S-1P is a dual-media tri-speed test module.


Dual-media tri-speed test module
The Loki-100G-3S-1P is a 3-speed (100/40/10GE) dual media test module for the ValkyrieCompact and ValkyrieBay chassis (where it occupies 2 slots).

This cost-optimized test module supports two transceiver form-factors: QSFP28 (CAUI-4), QSFP+ (CAUI), and CXP (CAUI) allowing users to choose either of these transceiver form factors to be active at any time.

When the CXP form-factor is selected, the user can, in addition to a single 100G test port, also use the test module to provide two 40G test ports or eight 10G test ports. This flexibility and price/performance makes it ideal for BERT, load-stress, and functional testing of Ethernet equipment and network infrastructure.

The Loki-100G-3S-1P dual-media tri-speed test module comes complete with a comprehensive suite of management and test application software.








Unique Eye Diagram
The Loki-100G-3S-1P includes a unique feature for analyzing signal quality called the “eye diagram”. When using CFP4 and QSFP28/QSFP+ ports on the Loki-100G-3S-1P, an additional panel called “Advanced PHY Features“ will appear in the main Resource Properties tab of ValkyrieManager. This panel controls and monitors the four receive SerDes associated with the 4x10G or 4x25G link at the physical level. It also creates bit-error-rate (BER) eye diagrams, estimates the link BER from the vertical and horizontal BER bathtub curves and controls the PHY tuning in the transmit and the receive directions.

How it works
The BER eye-diagram provides a direct visual representation of the signal quality after RX equalization. The eye-diagram is formed by changing the time dimension (sampling delay) and the amplitude dimension (0/1 threshold) of the sampling point of the PHY step-by-step. For each sampling point (x,y), 1 million bits are measured, the number of bit-errors are counted and a simple division gives the BER. The result is the BER eye-diagram (see below).

The color map shows the measured bit-error rate for each point going from 1 million (maximum red) to zero (black). The color scale is logarithmic. Higher resolutions give a clearer diagram and higher values of X and Y will also give a higher precision in the vertical and horizontal bathtub curve estimations, respectively.

What it shows
The eye-data table provides an estimate of several parameters of the eye, including width, height and jitter. Future releases will also include link BER estimates based on the horizontal and vertical bathtub curves.

Please see our wiki for more information on the “eye” diagram feature.



  • Dual-media support (QSFP28 or QSFP+ / CXP)
  • Tri-speed – 1 x 100G or 2 x 40G or 8 x 10G ports
  • Great price/performance
  • Testing flexibility
  • Ease of use
  • Unique “eye” diagram for signal analysis
  • Free software
  • Three years’ free SW updates
  • Three years’ free hardware warranty
  • Free tech support for product lifetime

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  1. Interface category

    CXP: 100G, 40G and 10G Ethernet
    QSFP28 : 100G Ethernet
    QSFP+ : 40G Ethernet

  2. Number of test ports

    CXP: 1 x 100G / 2 x 40G / 8 x 10G
    QSFP28: 1 x 100G
    QSFP+ : 1 x 40G

  3. Interface options

    CXP: 100GBASE-SR10, 40GBASE-iSR4 / 8 x 10GBASE-iSR(3)
    QSFP28: 100GBASE-SR4, 100GBASE-LR4, 100GBASE-CWDM4

  4. Forward Error Correction (FEC)

    RS-FEC (Reed Solomon) (528,514,t=7), IEEE 802.3 Clause 91

  5. Port statistics (2)

    Link state, FCS errors, pause frames, ARP/PING, error injections, training packet
    All traffic: RX and TX Mbit/s, packets/s, packets, bytes
    Traffic w/o test payload: RX and TX Mbit/s, packets/s, packets, bytes

  6. Adjustable Inter Frame Gap (IFG)

    Configurable from 16 to 56 bytes, default is 20B (12B IFG + 8B preamble)

  7. Transmit line rate adjustment

    Ability to adjust the effective line rate by forcing idle gaps equivalent to -1000 ppm (increments of 10 ppm)

  8. Transmit line clock adjustment

    From -400 to 400 ppm in steps of 0.001 ppm (shared across all ports)


    Supported (configurable IP and MAC address per port)

  10. Field upgradeable

    System is fully field upgradeable to product releases (FPGA images and Software)

  11. Histogram statistics (2)

    Two real-time histograms per port. Each histogram can measure one of RX/TX packet length, IFG, jitter, or latency distribution for all traffic, a specific stream, or a filter.

  12. Tx disable

    Enable/disable of optical laser or copper link

  13. IGMPv2 multicast join/leave

    IGMPv2 continuous multicast join, with configurable repeat interval

  14. Loopback modes

    • L1RX2TX – RX-to-TX, transmit byte-by-byte copy of the incoming packet
    • L2RX2TX – RX-to-TX, swap source and destination MAC addresses (1)
    • L3RX2TX – RX-to-TX, swap source and destination MAC addresses and IP addresses (1)
    • TXON2RX – TX-to-RX, packet is also transmitted from the port
    • TXOFF2RX – TX-to-RX, port’s transmitter is idle
    • Port-to-port – Inline loop mode where all traffic is looped 100% transparent at L1

  15. Oscillator characteristics

    • Initial Accuracy is 3 ppm
    • Frequency drift over 1st year: +/- 3 ppm (over 15 years: +/- 15 ppm)
    • Temperature Stability: +/- 20 ppm (Total Stability is +/- 35 ppm)


  1. Payload Test pattern

    PRBS 2^31

  2. Error Injection

    Manual single shot bit-errors or bursts, automatic continuous error injection

  3. Alarms

    Pattern loss, bit-error rate threshold

  4. Error analysis

    bit-errors: seconds, count, rate

  5. PCS virtual lane configuration

    User defined skew insertion per Tx virtual lane, and user defined virtual lane to SerDes mapping for testing of the Rx PCS virtual lane re-order function.

  6. PCS virtual lane statistics

    Relative virtual lane skew measurement (up to 2048 bits), sync header and PCS lane marker error counters, indicators for loss of sync header and lane marker, BIP8 errors


  1. Number of transmit streams per port

    256 (wire-speed)

  2. Test payload insertion per stream

    Wire-speed packet generation with timestamps, sequence numbers, and data integrity signature optionally inserted into each packet.

  3. Stream statistics (2)

    TX Mbit/s, packets/s, packets, bytes, FCS error

  4. Bandwidth profiles

    Burst size and density can be specified. Uniform and bursty bandwidth profile streams can be interleaved

  5. Field modifiers

    16-bit or 32-bit header field modifiers with inc, dec, or random mode. Each modifier has configurable bit-mask, repetition, min, max, and step parameters. 6 16-bit modifiers per stream or 3 32-bit modifiers per stream.

  6. Packet length controls

    Fixed, random, butterfly, and incrementing packet length distributions. Packet length from 56 to 12288 bytes

  7. Packet payloads

    Repeated user specified 1 to 18B pattern, an 8-bit incrementing pattern

  8. Error generation

    Undersize length (56B min) and oversize length (12288 max.) packet lengths, injection of sequence, misorder, payload integrity, and FCS errors

  9. TX packet header support and RX autodecodes

    Ethernet, Ethernet II, VLAN, ARP, IPv4, IPv6, UDP, TCP, LLC, SNAP, GTP, ICMP, RTP, RTCP, STP, MPLS, PBB, or fully specified by user

  10. Pause Frames

    Responds to incoming pause frames

  11. Packet scheduling modes

    • Normal (stream interleaved mode). Standard scheduling mode, precise rates, minor variation in packet inter-frame gap.
    • Strict Uniform. New scheduling mode, with 100% uniform packet inter-frame gap, minor deviation from configured rates
    • Sequential packet scheduling (sequential stream scheduling). Streams are scheduled continuously in sequential order, with configurable number of packets per stream
    • Burst. Packets per stream are organized in bursts. Bursts from active streams form a burst group. The user specifies time from start of one burst group till start of next burst group.


  1. Number of traceable Rx streams per port

    2016 (wire-speed)

  2. Automatic detection of test payload for received packets

    Real-time reporting of statistics and latency, loss, payload integrity, sequence error, and misorder error checking

  3. Jitter measurement

    Jitter (Packet Delay Variation) measurements compliant to MEF10 standard with 8 ns accuracy. Jitter can be measured on up to 32 streams.

  4. Stream statistics (2)

    • RX Mbit/s, packets/s, packets, bytes.
    • Loss, payload integrity errors, sequence errors, misorder errors
    • Min latency, max latency, average latency
    • Min jitter, max jitter, average jitter
    • ARP, ping, pause, gap


  5. Latency measurements accuracy

    ±64 ns (opto/elec).

  6. Latency measurement resolution

    8 ns (Latency measurements can calibrate and remove latency from transceiver modules)

  7. Number of filters:

    • 4 x 64-bit user-definable match-term patterns with mask, and offset
    • 4 x frame length comparator terms (longer, shorter)
    • 4 x user-defined filters expressed from AND/OR’ing of the match and length terms.

  8. Filter statistics (2)

    Per filter: RX Mbit/s, packets/s, packets, bytes.


  1. Capture criteria

    All traffic, stream, FCS errors, filter match, or traffic without test payloads

  2. Capture start/stop triggers

    Capture start and stop trigger: none, FCS error, filter match

  3. Capture limit per packet

    16 – 12288 bytes

  4. Wire-speed capture buffer per port

    256 kB for 100G
    128 kB for 40G

  5. Low speed capture buffer per port (10Mbit/sec)

    4096 packets (any size)


  1. Transmit Equalization Controls

    – Tx Transmit Equalization Controls Pre-emphasis
    – Tx Attenuation
    – Tx Post-emphasis Signal Integrity Analysis Graphical “eye” diagram
    – Rx Optional Auto-Tune of PHY 25Gbps Rx SerDes

  2. Signal Integrity Analysis

    – Graphical “eye” diagram
    – Horizontal bathtub curve estimation
    – Vertical bathtub curve estimation
    – Bit Error Rate (BER) estimation

  3. (1) Only at 10G

    (2) Counter size: 64 bits

    (3) iSR4 – where “i” represents interoperability between the QSFP+ transceiver with any 10GBASE-SR compliant modules

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