Thor-100G-5S-4P

Thor-100G-5S-4P is a 5-speed (100GE, 50GE, 40GE, 25GE, 10GE) dual media test module with the unique capability of being able to test both PAM4 and NRZ speeds.

software

Xena’s Thor-100G-5S-4P test module can test five different Ethernet network speeds – 100GE, 50GE, 40GE, 25GE and 10GE. This unique flexibility is provided via two physical transceiver cages – one supporting QSFP-DD/56/28/+ transceivers, and the other supporting QSFP56/28/+ transceivers.

The QSFP-DD cage can support the following speeds and ports: 1x100G, 2x100G, 4x100G, 2x50G, 4x50G, 8x 50G, 1x40G, 4x25G, and 4x10G Ethernet test ports. The QSFP56 cage can support the exact same speeds except for 4x100G or 8x50G Ethernet. Both cages can be active simultaneously except when the QSFP-DD cage runs 4x100G or 8x50G.

Thor-100G-5S-4P is the only test module on the market that can test both NRZ & PAM4 speeds, plus perform Auto-Negotiation and Link Training (AN/LT) with a comprehensive level of interoperability testing.

The result is a highly versatile solution for performance and functional testing of network infrastructure and Ethernet equipment that support 100GE including switches, routers, NICs, TAPs, packet-brokers, and backhaul platforms.

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Specifications

PORT LEVEL FEATURES

  1. Interface category

    QSFP-DD – 100G, 50G Ethernet
    QSFP56 – 100G, 50G Ethernet
    QSFP28 – 100G, 50G, 40G*, 25GE and 10G* Ethernet
    QSFP+ – 40G, 10G Ethernet

  2. Total number of test ports

    4x100G, 8x50G, 2x40G, 8x25G, and 8x10G Ethernet

  3. Interface options

    QSFP-DD cage

    • 4 x 100GBASE-CR2, or 4 x 100GBASE-DR (PAM4 / 802.3cd)
    • 2 x 100GBASE-SR2/CR2, 2 x 100GBASE-DR (PAM4 / 802.3cd (dual CS connector)
    • 1 x 100GBASE-SR4/LR4/CR4 (NRZ / 802.3bj)
    • 8 x 50GBASE-SR/CR (PAM4 / 802.3cd)
    • 4 x 50GBASE-SR/CR, (PAM4 / 802.3cd)
    • 2 x 50GBASE-SR2/LR2/CR2 (NRZ /  Consortium**)
    • 1 x 40GBASE-SR4/LR4/CR4 (NRZ / 802.3ba)
    • 4 x 25GBASE-SR/LR/CR (NRZ / 802.3by/Consortium**)
    • 4 x 10GBASE-SR/LR/CR (NRZ / 802.3ae)

    For the QSFP56 cage  – same as QSFP-DD minus support for 4 x 100GBASE-DR, 4 x 100GBASE-CR2 and 8 x 50GBASE-SR/C

     

    Actual interface options depend on the capabilities of the inserted transceiver. Both cages can be active simultaneously except when the QSFP-DD cage runs 4 x 100GBASE-DR or 8 x 50GBASE-SR/CR. Both cages must run with the same base interface configuration (e.g. 2 x 50G). Power capacity per QSFP-DD/QSFP56 cage: 15 watts.

    ** As defined by 25/50 Gigabit Ethernet Consortium

  4. Auto Negotiation and Link Training

    • IEEE 802.3 Clause 73, Auto-negotiation

    • IEEE 802.3 Clause 72, Link training

  5. Forward Error Correction (FEC)

    Forward Error Correction (FEC) RS-FEC (Reed Solomon) (528,514,t=7), IEEE 802.3 Clause 91 (100GE)
    RS-FEC (Reed Solomon) (544,514,t=15), IEEE 802.3 Clause 134 (100GE/50GE 802.3cd)
    RS-FEC (Reed Solomon) (528,514,t=7), IEEE 802.3 Clause 108 (25GE)
    RS-FEC (Reed Solomon) (528,514,t=7), 25/50G Ethernet Consortium (25/50GE)

  6. Port statistics (counter size: 64 bits)

    • Link state, FCS errors, pause frames, ARP/PING, error injections, training packet
    • All traffic: RX and TX Mbit/s, packets/s, packets, bytes
    • Traffic w/o test payload: RX and TX Mbit/s, packets/s, packets, bytes

  7. Adjustable Inter Frame Gap (IFG)

    Configurable from 16 to 56 bytes, default is 20B (12B IFG + 8B preamble)

  8. Transmit line rate adjustment

    Ability to adjust the effective line rate by forcing idle gaps equivalent to -1000 ppm (increments of 10 ppm)

  9. Transmit line clock adjustment

    Transmit line clock adjustment From -100 to 100 ppm in steps of 0.001 ppm (shared across all ports)

  10. ARP/PING

    Supported (configurable IP and MAC address per port)

  11. Field upgradeable

    System is fully field upgradeable to product releases (FPGA images and software)

  12. Histogram statistics (counter size: 64 bits)

    Two real-time histograms per port. Each histogram can measure one of RX/TX packet length, IFG, jitter,
    or latency distribution for all traffic, a specific stream, or a filter

  13. Tx disable

    Enable/disable of optical laser or copper link

  14. IGMPv2 multicast join/leave

    IGMPv2 continuous multicast join, with configurable repeat interval

  15. Loopback modes

    • L1RX2TX – RX-to-TX, transmit byte-by-byte copy of the incoming packet
    • L2RX2TX – RX-to-TX, swap source and destination MAC addresses (*only at 10G)
    • L3RX2TX – RX-to-TX, swap source and destination MAC addresses and IP addresses (*only at 10GE)
    • TXON2RX – TX-to-RX, packet is also transmitted from the port
    • TXOFF2RX – TX-to-RX, port’s transmitter is idle
    • Port-to-port – Inline loop mode where all traffic is looped 100% transparent at L1

  16. Oscillator characteristics

    • Initial Accuracy is 3 ppm
    • Frequency drift over 1st year: +/- 3 ppm (over 15 years: +/- 15 ppm)
    • Temperature Stability: +/- 20 ppm (Total Stability is +/- 35 ppm)

100/50/40/25GE FRAMED PRBS AND PCS LAYERS

  1. Payload Test pattern

    PRBS-7, PRBS-9, PRBS-10, PRBS-11, PRBS-13, PRBS-15, PRBS-20, PRBS-23, PRBS-31, PRBS-49, PRBS-58

  2. Error Injection

    Manual single shot bit-errors or bursts, automatic continuous error injection (coming)

  3. Alarms

    Pattern loss

  4. Error analysis

    Bit-errors: seconds, count, rate

  5. PCS virtual lane configuration

    User-defined skew insertion per Tx virtual lane, and user defined virtual lane to SerDes mapping for testing of the Rx PCS virtual lane re-order function. (coming)

  6. PCS virtual lane statistics

    Relative virtual lane skew measurement (up to 2048 bits)
    PAM4: Corrected Bit error, PreFEC BER
    NRZ, No FEC: sync header and PCS lane marker error counters, indicators for loss of sync header and lane marker, BIP8 errors

  7. FEC Total Statistics

    PAM4: Total corrected FEC symbols, Total uncorrected FEC symbols, Estimated Pre-FEC BER, Estimated Post-FEC BER, Pre-FEC Error Distribution Graph

  8. Link Flap

    Single short or repeatable link down events with ms precision

TRANSMIT ENGINES

  1. Number of transmit streams per port

    Initially 256 (wire-speed). Each stream can generate millions of traffic flows using field modifiers

  2. Test payload insertion per stream

    Wire-speed packet generation with timestamps, sequence numbers, and data integrity signature optionally inserted into each packet.

  3. Stream statistics

    TX Mbit/s, packets/s, packets, bytes, FCS error

  4. Bandwidth profiles

    Burst size and density can be specified. Uniform and bursty bandwidth profile streams can be interleaved

  5. Field modifiers

    16-bit or 32-bit header field modifiers with inc, dec, or random mode. Each modifier has configurable bit-mask, repetition, min, max, and step parameters. 8 16-bit modifiers per stream or 4 32-bit modifiers per stream

  6. Packet length controls

    Fixed, random, butterfly, and incrementing packet length distributions from 56 to 12288 bytes

  7. Packet payloads (basic)

    Repeated user specified 1 to 18B pattern, an 8-bit incrementing pattern

  8. Error generation

    Undersize length (56 bytes min) and oversize length (12288 bytes max.) packet lengths, injection of sequence, misorder, payload integrity, and FCS errors

  9. TX packet header support and RX autodecodes

    Ethernet, Ethernet II, VLAN, ARP, IPv4, IPv6, UDP, TCP, LLC, SNAP, GTP, ICMP, RTP, RTCP, STP, MPLS, PBB, or fully specified by user

  10. Packet scheduling modes

    • Normal (stream interleaved mode) – standard scheduling mode, precise rates, minor variation in packet inter-frame gap.
    • Strict Uniform – new scheduling mode, with 100% uniform packet inter-frame gap, minor deviation from configured rates.
    • Sequential packet scheduling (sequential stream scheduling). Streams are scheduled continuously in sequential order, with configurable number of packets per stream.
    • Burst. Packets in a stream are organized in bursts. Bursts from active streams form a burst group. The user specifies time from start of one burst group till start of next burst group.

RECEIVE ENGINE

  1. Number of traceable Rx streams per port

    2016 (wire-speed)

  2. Automatic detection of test payload for received packets

    Real-time reporting of statistics and latency, loss, payload integrity

    Coming: sequence error, and misorder error checking

  3. Jitter measurement

    Jitter (Packet Delay Variation) measurements compliant to MEF10 standard with 8 ns accuracy
    Jitter can be measured on up to 32 streams

  4. Stream statistics

    • RX Mbit/s, packets/s, packets, bytes.
    • Loss, payload integrity errors, (coming: sequence errors, misorder errors)
    • Min latency, max latency, average latency
    • Min jitter, max jitter, average jitter
  5. Latency measurements accuracy

    ±32 ns

  6. Latency measurement resolution

    8 ns (Latency measurements can calibrate and remove latency from transceiver modules)

  7. Number of filters:

    • 6 (100G/50G PAM4: 4) x 64-bit user-definable match-term patterns with mask, and offset
    • 6 (100G/50G PAM4: 4) x frame length comparator terms (longer, shorter)
    • 6 (100G/50G PAM4: 4) x user-defined filters expressed from AND/OR’ing of the match and length terms.
  8. Filter statistics

    Per filter: RX Mbit/s, packets/s, packets, bytes.

CAPTURE

  1. Capture criteria

    All traffic, stream, FCS errors, filter match, or traffic without test payloads

  2. Capture start/stop triggers

    Capture start and stop trigger: none, FCS error, filter match (coming)

  3. Capture limit per packet

    16 – 12288 bytes

  4. Wire-speed capture buffer per port

    384 kB for 400GE
    192 kB for 200GE
    96 kB for 100GE
    48 kB for 50GE
    48 kB for 40GE
    32 kB for 25GE
    16 kB for 10GE

  5. Low speed capture buffer per port (10Mbit/s speed)

    4096 packets (any size)

ADVANCED PHY FEATURES

  1. Equalization Controls

    Tx Transmit Equalization Controls:

    • Pre-emphasis
    • Tx Attenuation
    • Tx Post-emphasis Signal Integrity Analysis

    Optional Auto-Tune of Rx equalizer/CTLE

  2. Signal Integrity Analysis

    FEC error correction chart

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