Z1608 Edun

1.6Tbps (224G SerDes) traffic generator

software

Z1608 Edun is one of the world’s first Ethernet traffic generators for testing 224G PAM4 SerDes.

The Z1608 Edun comes with the OSFP-1600 interface and can be used with both optical cables, as well as active and passive cables.

The Z1608 Edun can be used for testing next-gen chips, Ethernet switches, routers, NICs, transceivers & cables helping developers optimize signal integrity and Bit Error Rate (BER) performance.

Providing the same UI and features as the existing Xena solutions (e.g. Z800 Freya), the Z1608 Edun boasts an extensive list of valuable features and functions for both advanced Layer 1 & Layer 2 testing. The extensive L1 features includes valuable insights into advanced PCS and PMA layer testing including dynamic transceiver clock sweep, lane skewing and PRBS modes.

There is also an advanced Signal Integrity View (SIV) to provide visual information on signal quality. The Layer 1 features can be combined with an enhanced Traffic Generator with advanced multi-stream support and functionalities such as latency and jitter statistics, modifiers, custom data fields and many other features.

The Z1608 Edun is a 1U chassis solution, making it the most compact and lightweight 224G tester in the market.

 

Advanced test software

Managing the Z1608 Edun is done using XenaManager, the intuitive multi-user management software for generating and analyzing traffic on all Teledyne LeCroy Xena modules.

Renowned for its ease-of-use, XenaManager makes it quick and easy to do performance, QA, functional and benchmark testing.

Xena OpenAutomation (XOA) – our open-source scripting and automation framework – is also included to help automate any available command to the system, with tailored tests, scripting and standardized test methodologies.

Plus there are standalone applications for testing RFC2544, RFC2889, RFC3918 and RFC1564.

 

“XIO” interface

Teledyne Lecroy’s Z1608 Edun provides a special “XIO” interface implemented using a USB-C connector with a proprietary pinout.

This connector allows external equipment full control of the complete management interface of the OSFP module inserted into the Z1608. All digital electrical signals of the OSFP connector are accessible, including the I2C management interface as well as the reset, module present and select, Low Power mode and interrupt.

The Z1608 is also able to adjust the voltage level of the 3.3V power supply to the OSFP module, and can measure the power consumption for the module as well as the temperature of the surroundings. Combining this with the flexibility of the XIO interface, facilitates extensive debugging and characterization of all aspects of the OSFP module, effectively eliminating the need for an external Module Compliance Board (MCB).

The pinout of the XIO USB-C connector is shown below. It has been designed to be symmetrical so an external cable cannot be inserted incorrectly, as is the case with the normal USB-C connector.

Z1608-Edun-XIO-diagram

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Specifications

PORT LEVEL FEATURES

  1. Number of module cages/connectors

    1 x OSFP-1600

  2. Interface Options

    • 1 x 1.6T* (PAM4 – 802.3dj)
    • 1 x 800G (PAM4 – 802.3dj)
    • 2 x 400G (PAM4 – 802.3d)
    • 4 x 200G (PAM4 – 802.3dj)
  3. Forward Error Correction (FEC)

    RS-FEC (Reed-Solomon) (544,514,t=15), IEEE802.3 Clause 176

  4. PMA Layer

    • SM-PMA Symbol multiplexing (Clause 176)
    • BM-PMA Bit multiplexing (Clause 120)
  5. Traffic generation

    Wire-speed multi-stream packet generation with advanced configuration options

  6. Port statistics

    • Link state, FCS errors, pause frames, ARP/PING, error injections, training packet
    • All traffic: RX and TX Mbit/s, packets/s, packets, bytes
    • Traffic w/o test payload: RX and TX Mbit/s, packets/s, packets, bytes
  7. Histogram statistics

    Two real-time histograms per port. Each histogram can measure one of RX/TX packet length, IFG, or Latency distribution for all traffic, a specific stream, or a filter

  8. Adjustable Inter FrameGap (IFG)

    Configurable from 16 to 63 bytes, default is 20B (12B IFG + 8B preamble)

  9. Transmit line rate adjustment

    Ability to adjust the effective line rate by forcing idle gaps equivalent to -1000 ppm (increments of 10 ppm)

  10. ARP/PING

    Supported (configurable IP and MAC address per port)

  11. IGMPv2 multicast join/leave

    IGMPv2 continuous multicast join, with configurable repeat interval

  12. LLDP

    • Detect incoming LLDP and show information received.
    • DUT LLDP frames function test (receive and transmit)
  13. Tx disable

    Enable/disable of optical laser or copperlink

  14. Loopback modes

    • L1RX2TX – RX-to-TX, transmit byte-by-byte copy of the incoming packet
    • TXON2RX – TX-to-RX, packet is also transmitted from the port
    • TXOFF2RX – TX-to-RX, port’s transmitter is idle
    • Port-to-port – Inline loop mode where all traffic is looped 100% transparent at L1

PCS/PMA LAYERS TESTING

  1. Payload Test pattern

    PRBS-13Q, PRBS-31Q, SSPRQ test pattern (IEEE 802.3 Clause 120.5.11.2.3) and Square Wave (IEEE 802.3 Clause 120.5.11.2.4).

  2. Alarms

    PRBS pattern loss, link sync loss

  3. Error analysis

    Bit-errors: seconds, count, rate

  4. PCS virtual lane configuration

    User-defined skew insertion per Tx virtual lane, and user-defined virtual lane-to-SerDes mapping for testing of the Rx PCS virtual lane reorder function

  5. PCS virtual lane statistics

    Relative virtual lane skew measurements (up to 2048 bits)

    Corrected Bit error, Pre-FEC BER

  6. FEC error injection

    • Advanced FEC error injection in FEC Codewords
    • Advanced FEC error injection in FEC Symbols

    Option to choose:

    • Max Consecutive Uncorrectable w/o Link Loss
    • Min Consecutive Uncorrectable with Link Loss

    Statistics for: injected FEC errors; Total Codewords, Total Uncorrectable Codewords, Total Correctable Codewords, Total error-free Codewords, Codeword error ratio and Total Symbol Errors

  7. FEC Total statistics

    Total corrected FEC symbols,Total uncorrected FEC symbols, Estimated Pre-FEC BER, Estimated Post-FEC BER, Pre-FEC Error Distribution Graph

  8. Link Flap

    Single shot or repeatable link-down events with ms precision

  9. Error Injection (PMA Layer)

    Repeatable error inject periods at PMA layer with ms precision

ADVANCED PHY FEATURES

  1. Equalization Controls

    Tx Transmit Equalization Controls

    • Pre-emphasis
    • Attenuation
    • Post-emphasis

    Rx Receive Equalization Controls

    • Tap Freeze or Auto tune
    • Continuous Time Linear Equalizer

     

  2. Signal Integrity Analysis

    Advanced Signal Integrity View for PAM4 modulated signal quality analysis

TRANSMIT ENGINES

  1. Number of transmit streams per port

    256 (wire-speed)

    Each stream can generate millions of traffic flows using field modifier.

  2. Test payload insertion per stream

    Wire-speed packet generation with timestamps, sequence numbers, and data integrity signature optionally inserted into each packet

  3. Stream statistics

    TX Mbit/s, packets/s, packets, bytes, FCS error

  4. Bandwidth profiles

    Burst size and density can be specified. Uniform and bursty bandwidth profile streams can be interleaved.

  5. Field modifiers

    24-bit header field modifiers with incremental, decremental, or random mode.

    Each modifier has configurable bit-mask, repetition, min, max, and step parameters in TGA mode. Eight 24-bit modifiers can be configured per stream

  6. Packet length controls

    Fixed, random, butterfly, and incrementing packet length distributions from 56 to 16k bytes

  7. Packet payloads (basic)

    Repeated user-specified 1 to 18B pattern, an 8-bit incrementing pattern

  8. Error generation

    Undersize length (56 bytes min) and oversize length (12288 bytes max.) packet lengths, injection of sequence, misorder, payload integrity, and FCS errors

  9. TX packet header support and RX auto decodes

    Ethernet, Ethernet II, VLAN, ARP, IPv4, IPv6, UDP, TCP, LLC, SNAP, GTP, ICMP, RTP, RTCP, STP, MPLS, PBB, or fully specified by user.

  10. Packet scheduling modes

    • Normal (stream interleaved mode) – standard scheduling mode, precise rates, minor variation in packet inter-frame gap.
    • Strict Uniform – with 100% uniform packet inter-frame gap, minor deviation from configured rates is available in TGA mode.
    • Sequential packet scheduling (sequential stream scheduling) is available in TGA mode. Streams are scheduled continuously in sequential order, with configurable number of packets per stream.
    • Burst. Packets in a stream are organized in bursts. Bursts from active streams form a burst group is available in TGA mode. The user specifies time from start of one burst group till start of next burst group.

RECEIVE ENGINE

  1. Number of traceable Rx streams per port

    2016 (wire-speed)

  2. Automatic detection of test payload for received packets

    Real-time reporting of statistics and latency, loss, payload integrity, sequence error, and misorder error checking is available

  3. Packet Jitter measurement

    Jitter (Packet Delay Variation) measurements compliant to MEF10 standard with 1 ns accuracy. Jitter can be measured on up to 256 streams.

  4. Stream statistics 1)

    • RX Mbit/s, packets/s, packets, bytes
    • Loss, payload integrity errors, sequence errors, misorder errors
    • Min latency, max latency, average latency
    • Min jitter, max jitter, average jitter
  5. Latency measurements accuracy

    ±16 ns

  6. Latency measurement resolution

    1 ns (Latency measurements can calibrate and remove latency from transceiver modules)

  7. Number of filters

    • 6 x 64-bit user-definable match-term patterns with mask, and offset
    • 6 x frame length comparator terms (longer, shorter)
    • 6 x user-defined filters expressed from AND/OR’ing of the match and length terms
  8. Filter statistics

    Per filter: RX Mbit/s, packets/s, packets, bytes

  9. TX packet header support and RX auto decodes

    Ethernet, Ethernet II, VLAN, ARP, IPv4, IPv6, UDP, TCP, LLC, SNAP, GTP, ICMP, RTP, RTCP, STP, MPLS, PBB, or fully specified by user.

CAPTURE

  1. Capture criteria

    All traffic, stream, FCS errors, filter match, or traffic without test payloads

  2. Capture limit per packet

    16 – 16383 bytes

  3. Wire-speed capture buffer per port

    64 kB

  4. Low speed capture buffer per port (10Mbit/sec)

    4096 packets (any size)

EXTERNAL INTERFACES AND HW SPECIFICATIONS

  1. Transmit line clock adjustment

    From -400 to 400 ppm in steps of 1 ppm (shared across all ports)

  2. PPM Sweep

    Configurable linear or step sweep +/- 400 ppm

  3. Oscillator characteristics

    • Initial Accuracy is 3 ppm
    • Frequency driftover 1st year:+/- 3 ppm (over 15 years: +/- 15 ppm)
    • Temperature Stability: +/- 20 ppm (Total Stability is +/- 35 ppm)
  4. I2C RX/TX transceiver access speed

    To a maximum of 1MHz (actual speed depends on medium support)

  5. Clock input/output

    2,048MHz, 10.000MHz, 156.25MHz Clock input and Clock output to external equipment vis 2,4 mm SMA connector

  6. External Transceiver I/O

    Direct transceiver control through USB-C connection, using Xena specified protocol

  7. Connector insertions

    Xena uses high-quality 224Gbps-capable electrical OSFP connectors on Z1608 Edun modules for optimal signal integrity and performance. However, all connectors experience wear when inserted, resulting in decreased signal integrity over time.

    The OSFP Connectors provides a minimum of 1000 cycles where optimal signal integrity is guaranteed.

  8. Trigger and Sync

    In & Out for triggers and for sync between 2xZ1608 Edun’s – 2.4mm SMA Connector

SPECIFICIATIONS

  1. Design and Physical

    • 1 rack unit (RU) high with 1 module slots
    • 1“ (H) x 19“ (W) x 15“(D) (4.8 x 48.26 x 37cm)
    • 19″ rack mount (EIA compatible)
    • Front to rear airflow
  2. Weight

    13.89 lbs (6.3 kg)

  3. Environmental

    • Operating Temperature: 10 to 35ºC
    • Storage Temperature: -40 to 70ºC
    • Humidity: 8% to 90% non-condensing
  4. Noise

    Typical. 45dBa / Max. 55dBa

  5. Power

    • AC Voltage: 100-240V
    • Frequency: 50-60Hz
    • Max. Power: 600W
  6. Regulatory

    FCC (US),CE (Europe)

  7. User interface

    • Chassis power on/off
    • Management RJ45 Ethernet (100/1000M BASE-T)
      • IPv4 and IPv6 Static or DHCP
      • XenaManager (XM), XenaOpenAutomation (XOA) and XOA CLI
    • QR code links to detailed product guidance and collateral

Includes this free software

Technical Documentation