New Z800 Freya SW release delivers valuable features for testing 112G SerDes

News -

Release 2.15 is now available for Xena Z800 Freya Ethernet traffic generators.

In addition to general stability and performance improvements, Release 2.15 adds important new features to the Xena Z800 Freya traffic generators.



Release 2.15 contains these valuable new features:

  1. Supports traffic generation according to 1x800G ETC or 1x800G IEEE1x800G when running in AN/LT mode (single stream TGA without stream statistics)

  2. AN/LT expansions in XenaManager

  3. Signal Integrity View (SIV)

  4. Support for 2 new test patterns that complement the PRBS

  5. I2C access speed now up to 800KHz

  6. RS-FEC Support

Please note that the Freya 2.15 software is only applicable to Z800 Freya test modules. Existing Freya customers can request the software and full release notes by contacting us directly.

Below are details of the new functionalities in Freya 2.15. Alternatively, check out this 5 min video explaining how they work:

1. Support for both IEEE and ETC 800G-ETC-CR8/KR8

Both IEEE and ETC have different specifications for 100 Gb/s lane rate based 800GbE. As a result, you have to select which technology is going to be used for the link. So now when using XenaManager and the Z800 Freya to test 800G, you can manually configure the 800G variant by selecting IEEE or ETC, or let auto-negotiation decide.

2. AN/LT Expansions

XenaManager has been enhanced with a number of new ANLT capabilities:

Auto restart now offers 2 modes. The first is called: Enable ANLT Auto-Restart after Link Toggling. This will restart ANLT if the link is down, and ANLT will start again, until the link is up.

The second mode is called “Enable ANLT Auto-Restart after Link Training Failure”. If link training fails, ANLT will start again until link training succeeds. Link training success occurs when both link training ports are declared trained.

Link Training Timeout can be configured to let you enable or disable link training timeout. IEEE defines that ANLT need to be completed within 12 seconds, but for test purposes, the option to disable it can be useful.

The Technology and FEC Abilities configuration makes it easy to select the technology and FEC abilities that the port should advertise. The abilities the port supports are in bold. What is being configured are the 5 F bits in the auto negotiation frame, F0 to F4.

It is also possible to see the Tech Abilities the remote link partner advertises, for both speed and FEC abilities.

The Auto-Negotiation Results overview shows the results of the Auto-Negotiation, which includes if the Auto-Negotiation ended successfully, and which highest common denominator of the various technology abilities that were negotiated, including the FEC.

The Link Training Results overview shows the status of each of the SerDes, the status of Link training completion, the Link training duration from start to when both ends declare trained, the TX precoding config and the RX precoding status.

3. Signal Integrity View (SIV)

This new feature lets you easily analyze 112G PAM4 signal loss and noise impairments.

When a signal is transmitted from one port to another, several factors can degrade the signal. The signal level will be reduced due to the inherent resistance of the wires causing gradual loss of signal as the signal moves from the transmitter to the receiver. Bandwidth limitations will lead to Inter-Symbol Interference (ISI), while inductive coupling between electrical lanes and connectors will lead to cross talk. Similarly, impedance mismatches can cause reflections – also known as “Return Loss”. Jitter can occur at both the transmitter and receiver and finally thermal noise can also degrade the signal.

Signal integrity involves measuring of the quality of the transmitted signal and is commonly displayed as an eye-diagram.

However, when used for 112G SerDes PAM4 signals, the pre-FEC eye diagram is likely to be almost closed and difficult to use for analyzing signal integrity. Instead, a vertical slicer eye diagram can be used. This diagram is constructed by plotting the sampled, recovered signal level for a large number of samples.

The Signal Integrity View (below) in XenaManager clearly shows the sample view which are the effects of signal loss and noise, while the histogram view next to it shows the distribution shape of each slice. This makes it much easier to identify the characteristics of each eye slice.

You can use the Signal Integrity View control panel in XenaManager to quickly configure which SerDes to analyze, as well as the analysis period.

4. SSPRQ and Square Wave Test Pattern

These are two new test patterns supported by Z800 Freya.

The SSPRQ pattern – which stands for Short Stress Pattern Random Quaternary and is one of IEEE 802.3 Clauses – tries to find a balance between being short enough for capture while being more stressful than extended random data periods. Despite its stress-inducing nature, SSPRQ remains manageable for advanced Equalization, BER, Jitter and Noise analysis. This makes it suitable for optical and electrical transmitter compliance verification, and Clock recovery test in the data receiver.

5. I2C Access Speed – now up to 800KHz

With Release 2.15 the I2C access speed on Z800 Freya can now be configured from 100KHz up to 800KHz. The higher the frequency you configure, the faster you can read and write to registers in the transceiver inserted in the cage. This increases the efficiency of testing that involves transceiver configuration.

6. RS-FEC Support

And finally, Reed-Solomon Forward Error Correction – or RS-FEC – is now also an option when configuring a Z800 Freya port to 100GBASE with 112G SerDes lane speed.