Z800o Freya

5-speed 800G (56/112Gbps SerDes) & OSFP compatible test module

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The Z800o Freya test module supports these Ethernet network speeds – 800GE, 400GE, 200GE, and 100GE and 50GE using 56/112G SerDes (PAM4 56/112G).

The module supports OSFP-compatible transceivers and the following speeds: 1x800GE, 2 or x400GE, 4 or 2x200GE, 8 or 4x100GE or 8x50GE

Z800o Freya is a highly versatile solution for performance and functional testing of network infrastructure and Ethernet equipment including switches, routers, NICs, TAPs, packet-brokers, and backhaul platforms.

Z800o Freya is unique on the market with its ability to test up to 800GE with 112G SERDES (PAM4 112G) on OSFP optics and DACs and perform Auto-Negotiation and Link Training (AN/LT). Received signals can be analyzed the advanced signal integrity view, which provides visual information on the quality of the signal.

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Specifications

PORT LEVEL FEATURES

  1. Interface category

    OSFP: 800G, 400G, 200G, 100G, 50GE Ethernet

  2. Total number of test ports (software configurable)

    1x800G, 2x400G, 4x200G and 8x100G and 50G Ethernet

  3. Interface options

    OSFP cage:

    112G SerDes:

    1 x 800GE or                 PAM4         802.3df (D2.0) /Consortium**
    2 or 1 x 400GE or          PAM4         802.3ck or
    4 or 2 x 200GE or          PAM4         802.3ck or
    8 or 4 x 100GE              PAM4         802.3ck

     

    56G Serdes:

    1 x 400GE       PAM4          802.3bs or 802.3cd or
    2 x 200GE       PAM4          802.3cd or
    4 x 100GE       PAM4          802.3cd or
    8 x 50GE         PAM4          802.3cd

    Power capacity: 20W (XenaB2400) / 25W (XenaCompact)

    ** As defined by Ethernet Technology Consortium

  4. Auto Negotiation and Link Training

    Auto-negotiation: IEEE 802.3 Clause 73 and ETH. 400G/800G specifications
    Link training: IEEE 802.3 Clause 136 and 161

  5. Forward Error Correction (FEC)

    RS-FEC (Reed-Solomon) (544,514,t=15), IEEE802.3 Clause 119
    RS-FEC (Reed-Solomon) (544,514,t=15), IEEE802.3 Clause 134
    RS-FEC (Reed-Solomon) (544,514,t=15), IEEE802.3 Clause 161 for 100GBASE

  6. Number of transceiver module cages

    1 x OSFP

  7. Port statistics

    Link state, FCS errors, pause frames, ARP/PING, error injections, training packet
    All traffic: RX and TX Mbit/s, packets/s, packets, bytes
    Traffic w/o test payload: RX and TX Mbit/s, packets/s, packets, bytes

  8. Adjustable Inter Frame Gap (IFG)

    Configurable from 16 to 56 bytes, default is 20B (12B IFG + 8B preamble)

  9. Transmit line rate adjustment

    Ability to adjust the effective line rate by forcing idle gaps equivalent to -1000 ppm (increments of 10 ppm)

  10. Transmit line clock adjustment

    From -400 to 400 ppm in steps of 1 ppm (shared across all ports)

  11. PPM Sweep

    Configurable linear or step sweep +/- 400 ppm

  12. ARP/PING

    Supported (configurable IP and MAC address per port)

  13. Field upgradeable

    System is fully field upgradeable to product releases (FPGA images and software)

  14. Tx disable

    Enable/disable of optical laser or copper link

  15. IGMPv2 multicast join/leave

    IGMPv2 continuous multicast join, with configurable repeat interval

  16. Histogram statistics

    Two real-time histograms per port. Each histogram can measure one of RX/TX packet length, IFG, or Latency distribution for all traffic, a specific stream, or a filter

  17. Loopback modes

    • L1RX2TX – RX-to-TX, transmit byte-by-byte copy of the incoming packet
    • TXON2RX – TX-to-RX, packet is also transmitted from the port
    • TXOFF2RX – TX-to-RX, port’s transmitter is idle

  18. Oscillator characteristics

    • Initial Accuracy is 3 ppm
    • Frequency drift over 1st year: +/- 3 ppm (over 15 years: +/- 15 ppm)
    • Temperature Stability: +/- 20 ppm (Total Stability is +/- 35 ppm)

  19. I2C RX/TX transceiver access speed

    To a maximum of 800KHz (actual speed depends on medium support)

  20. Electrical cables

    Both Passive and Active electrical cables are supported:

    • DACs tested up to 2,5-meter cable*
    • ACCs tested up to 4-meter cable*
    • AECs tested up to 7-meter cable*

    *Length might variate dependent on vendor

PCS/PMA LAYERS TESTING

  1. Payload Test pattern

    PRBS-13Q, PRBS-31Q, SSPRQ test pattern (IEEE 802.3 Clause 120.5.11.2.3) and Square Wave (IEEE 802.3 Clause 120.5.11.2.4).

  2. Alarms

    PRBS pattern loss, link sync loss

  3. Error analysis

    Bit-errors: seconds, count, rate

  4. PCS virtual lane configuration

    User-defined skew insertion per Tx virtual lane, and user defined virtual lane to SerDes mapping for testing of the Rx PCS virtual lane re-order function

  5. PCS virtual lane statistics

    Relative virtual lane skew measurements (up to 2048 bits)
    Corrected Bit error, PreFEC BER

  6. FEC Total statistics

    Total corrected FEC symbols, Total uncorrected FEC symbols, Estimated Pre-FEC BER, Estimated Post-FEC BER, Pre-FEC Error Distribution Graph

  7. Link Flap

    Single short or repeatable link down events with ms precision

  8. Error Injection (PMA Layer)

    Repeatable error inject periods at PMA layer with ms precision

PHY/TRANSCEIVER ETHERNET TESTING

  1. Programmable Pattern Generator

    Supported in Layer 1/ANLT mode:

    • Single stream Ethernet frames with FCS
    • Traffic load: up to 100%
    • Configurable Frame Size distribution and content
    • Transmit and Receive Statistics
    • No latency and jitter measurement, No Filter and No capture supported

ADVANCED PHY FEATURES

  1. Equalization Controls

    Tx Transmit Equalization Controls

    • Pre-emphasis
    • Attenuation
    • Post-emphasis

     

    Rx Receive Equalization Controls

    • Continuous Time Linear Equalizer

  2. Signal Integrity Analysis

    • Advanced Signal Integrity View for PAM4 modulated signal quality analysis

TRANSMIT ENGINES

  1. Number of transmit streams per port

    256 (wire-speed)
    Each stream can generate millions of traffic flows using field modifiers

  2. Test payload insertion per stream

    Wire-speed packet generation with timestamps, sequence numbers, and data integrity signature optionally inserted into each packet.

  3. Stream statistics

    TX Mbit/s, packets/s, packets, bytes, FCS error

  4. Bandwidth profiles

    Burst size and density can be specified. Uniform and bursty bandwidth profile streams can be interleaved

  5. Field modifiers

    24-bit header field modifiers with incremental, decremental, or random mode. Eachmodifier has configurable bit-mask, repetition, min, max, and step parameters. Eight 24-bit modifiers can be configured per stream

  6. Packet length controls

    Fixed, random, butterfly, and incrementing packet length distributions from 56 to 16k bytes

  7. Packet payloads (basic)

    Repeated user specified 1 to 18B pattern, an 8-bit incrementing pattern

  8. Error generation

    Undersize length (56 bytes min) and oversize length (12288 bytes max.) packet lengths, injection of sequence, misorder, payload integrity, and FCS errors

  9. TX packet header support and RX autodecodes

    Ethernet, Ethernet II, VLAN, ARP, IPv4, IPv6, UDP, TCP, LLC, SNAP, GTP, ICMP, RTP, RTCP, STP, MPLS, PBB, or fully specified by user

  10. Packet scheduling modes

    • Normal (stream interleaved mode) – standard scheduling mode, precise rates, minor variation in packet inter-frame gap.
    • Strict Uniform – new scheduling mode, with 100% uniform packet inter-frame gap, minor deviation from configured rates.
    • Sequential packet scheduling (sequential stream scheduling). Streams are scheduled continuously in sequential order, with configurable number of packets per stream.
    • Burst. Packets in a stream are organized in bursts. Bursts from active streams form a burst group. The user specifies time from start of one burst group till start of next burst group.

RECEIVE ENGINE

  1. Number of traceable Rx streams per port

    2016 (wire-speed)

  2. Automatic detection of test payload for received packets

    Real-time reporting of statistics and latency, loss, payload integrity, sequence error, and misorder error checking

  3. Jitter measurement

    Jitter (Packet Delay Variation) measurements compliant to MEF10 standard with 1 ns accuracy
    Jitter can be measured on up to 32 streams

  4. Stream statistics

    • RX Mbit/s, packets/s, packets, bytes.
    • Loss, payload integrity errors, sequence errors, misorder errors
    • Min latency, max latency, average latency
    • Min jitter, max jitter, average jitter

  5. Latency measurements accuracy

    ±16 ns

  6. Latency measurement resolution

    1 ns (Latency measurements can calibrate and remove latency from transceiver modules)

  7. Number of filters:

    • 6 x 64-bit user-definable match-term patterns with mask, and offset
    • 6 x frame length comparator terms (longer, shorter)
    • 6 x user-defined filters expressed from AND/OR’ing of the match and length terms

  8. Filter statistics

    Per filter: RX Mbit/s, packets/s, packets, bytes

  9. Rx Tap Settings

    Freeze or Auto tune

CAPTURE

  1. Capture criteria

    All traffic, stream, FCS errors, filter match, or traffic without test payloads

  2. Capture limit per packet

    16 – 12288 bytes

  3. Wire-speed capture buffer per port

    64 kB

  4. Low speed capture buffer per port (10Mbit/s speed)

    4096 packets (any size)

HW SPECIFICATIONS

  1. Max. Power

    TBA

  2. Weight

    2.31 lbs (1.05 kg)

  3. Environmental

    Operating Temperature: 10 to 35º C
    Storage Temperature: -40 to 70º C
    Humidity: 8% to 90% non-condensing

  4. Regulatory

    FCC (US), CE (Europe)

  5. Connector insertions

    Xena uses high-quality 112Gbps-capable electrical connectors on Freya modules foroptimal signal integrity and performance. However, all connectors experience wear wheninserted, resulting in decreased signal integrity over time. The specification below is theminimum number of insertions where optimal signal integrity is guaranteed:

    Connector for OSFP:
    Minimum number of guaranteed insertions: 500 cycles

  6. Notes

    This module is only supported by the B2400 / Val-C12-2400 and the XenaCompact chassis
    This module requires two slots in the B2400 / Val-C12-2400 chassis

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Technical Documentation

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