SmartNIC ASIC Performance

Background

Smart Network Interface Cards (SmartNICs) are used in large data centers to off-load networking services from the Server CPUs. This is a cost and energy efficient strategy that improves scalability and security for organizations running large data centers.

Unlike traditional NICs, SmartNICs offer programmable packet processing, storage, and networking functionality. They can also monitor key network performance parameters like latency, speed, throughput, and packet loss. SmartNIC interface speeds are typically 100Gbps and above.

Recently, a Chinese high-tech startup focused on cloud data center ASIC product development was developing network interconnect ASICs for SmartNICs used in large scale data centers and cloud computing.

To verify the performance of their new ASIC, the company needed a network emulator.

The Challenge

The ability to detect and correct various network impairments is a crucial function of the SmartNIC ASIC. For instance, bit errors are corrected by the Forward Error Correction, short link failures are detected and repaired, out-of-order packets are re-ordered, and latency and jitter are measured. As part of the product development, the Chinese vendor needed to verify the performance of the ASIC when exposed to various network impairments.

It is important that the impairments can be inserted accurately and precisely. For example, to accurately verify the performance of the FEC function, bit errors need to be inserted randomly at the physical layer in a controlled manner. Because the ASIC can detect and repair very short link failures, it is also important to emulate such short link flaps very accurately.

Up until then, the Chinese vendor had used software-based testers for verification testing. However, these solutions did not have the performance and accuracy required to insert impairments to fully verify the performance of their implementation.

The Solution

The company therefore decided to try the Teledyne LeCroy Xena E100 Chimera network emulator in their Beijing R&D Center to evaluate if it could deliver the desired accuracy and precision they needed.

The E100q Chimera can emulate a broad range of network impairments like latency, jitter, packet and port impairments, flexible distributions, and BW shaping. These impairments can be done at five Ethernet speeds: 100GE, 50GE, 40GE, 25GE and 10GE. This flexibility is provided via two physical transceiver cages, both supporting QSFP28 and QSFP+ transceivers.

The result is a versatile solution that provides consistent, accurate, well-defined, and repeatable impairments to traffic between network equipment in the lab.

E100q Chimera is ideal for impairment testing of network infrastructure with Ethernet ports capable of supporting up to 100GE, and the device is easily controlled using the GUI-based XenaManager software.

Using the E100 Chimera’s powerful PMA layer error injection function, and its random injection model, the company was able to realistically introduce bit errors to simulate real-world network impairment scenarios.

To verify the ASICs capability to detect a link outage above 10ms, E100 Chimera was used to insert a link flap of precisely 9ms and 11ms, respectively. This test confirmed that the ASIC recovered from the 11ms link outage as expected.

Another important function of the SmartNIC ASIC is to correct out-of-order packet sequences arising from, for instance, load balancing.

The E100 Chimera makes it easy to arrange a deliberate wrong ordering of packets as shown on Figure 1. By transmitting this packet sequence through the SmartNIC ASIC, the vendor could quickly confirm that the new ASIC corrected the out-of-order sequence (Figure 2).

The E100 Chimera impairment tester also allowed the delay and jitter of various distribution models to be emulated with high accuracy. Delay impairments from the microsecond to the second level at wire speed were inserted. In this way, it was possible to accurately test the impact of different delays of ASICS and smart network cards.

SUMMARY

SmartNICs are replacing traditional NICs in large datacenters to improve scalability and security. By incorporating programmable packet processing, storage, and networking functionality, SmartNICs can off-load networking services from the server CPU. Furthermore, SmartNICs are designed to monitor and recover from key network impairments.

A Chinese vendor developing ASICs for SmartNICs needed an accurate and precise, hardware-based test solution to verify their product design. Previously, they had used a software-based tester but that was not accurate enough.

The E100 Chimera was a very cost-effective network emulation solution that made it easy for them to fully verify the performance of their product and thereby offer a better product for their customers.