Freya-800G-1S-1P-OSFP

4-speed 800G (112Gbps SerDes) & OFSP compatible test module

software

The Freya-800G-1S-1P-OSFP test module supports four Ethernet network speeds – 800GE, 400GE, 200GE and 100GE using 112G SerDes (PAM4 112G).

The module supports OSFP-compatible transceivers and the following speeds: 1x800GE, 2x400GE, 4x200GE and 8x100GE.

Freya-800G-1S-1P-OSFP is a highly versatile solution that provides comprehensive PCS and PMA layer test capabilities facilitates thorough transceiver and PHY testing. This includes the advanced signal integrity view, which provides visual information on the quality of the received signal.

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Specifications

PORT LEVEL FEATURES

  1. Interface category

    OSFP 800G, 400G, 200G, 100G Ethernet

  2. Total number of test ports (software configurable)

    1x800G, 2x400G, 4x200G and 8x100G Ethernet

  3. Interface options

    OSFP cage:

    1 x 800GE or           PAM4       Consortium**
    2 x 400GE or           PAM4           802.3ck
    4 x 200GE or           PAM4           802.3ck
    8 x 100GE or           PAM4           802.3ck

    Power capacity of OSFP cage: 15W (ValkyrieBay) / 25W (ValkyrieCompact).

    ** As defined by Ethernet Technology Consortium

  4. Auto Negotiation and Link Training

    IEEE 802.3 Clause 73, Consortium 800G specification, Auto-negotiation
    IEEE 802.3 Clause 72, Link training

  5. Forward Error Correction (FEC)

    RS-FEC (Reed Solomon) (544,514,t=15), IEEE 802.3 Clause 119, Clause 134

  6. Number of transceiver module cages

    1 x OSFP

  7. Port statistics

    Link state, FCS errors, RX and TX Mbit/s, packets/s, packets, bytes

  8. Adjustable Inter Frame Gap (IFG)

    Configurable from 16 to 56 bytes, default is 20B (12B IFG + 8B preamble)

  9. Transmit line rate adjustment

    Ability to adjust the effective line rate by forcing idle gaps equivalent to -1000 ppm (increments of 10 ppm)

  10. Transmit line rate adjustment

    Ability to adjust the effective line rate by forcing idle gaps equivalent to -1000 ppm (increments of 10 ppm)

  11. Transmit line clock adjustment

    From -400 to 400 ppm in steps of 0.001 ppm (shared across all ports)

  12. Field upgradeable

    System is fully field upgradeable to product releases (FPGA images and software)

  13. Tx disable

    Enable/disable of optical laser or copper link

  14. Loopback modes

    • L1RX2TX – RX-to-TX, transmit byte-by-byte copy of the incoming packet
    • TXON2RX – TX-to-RX, packet is also transmitted from the port
    • TXOFF2RX – TX-to-RX, port’s transmitter is idle
  15. Oscillator characteristics

    • Initial Accuracy is 3 ppm
    • Frequency drift over 1st year: +/- 3 ppm (over 15 years: +/- 15 ppm)
    • Temperature Stability: +/- 20 ppm (Total Stability is +/- 35 ppm)

PCS/PMA LAYERS TESTING

  1. Payload Test pattern

    PRBS-31Q

  2. Alarms

    PRBS pattern loss, link sync loss

  3. Error analysis

    Bit-errors: seconds, count, rate

  4. PCS virtual lane configuration

    User-defined skew insertion per Tx virtual lane, and user defined virtual lane to SerDes mapping for testing of the Rx PCS virtual lane re-order function

  5. PCS virtual lane statistics

    Relative virtual lane skew measurements (up to 2048 bits)
    Corrected Bit error, PreFEC BER

  6. FEC Total statistics

    Total corrected FEC symbols, Total uncorrected FEC symbols, Estimated Pre-FEC BER, Estimated Post-FEC BER, Pre-FEC Error Distribution Graph

  7. Link Flap

    Single short or repeatable link down events with ms precision

  8. Error Injection (PMA Layer)

    Repeatable error inject periods at PMA layer with ms precision

PCS/PMA LAYERS TESTING

  1. Payload Test pattern

    PRBS-31Q

  2. Alarms

    PRBS pattern loss, link sync loss

  3. Error analysis

    Bit-errors: seconds, count, rate

  4. PCS virtual lane configuration

    User-defined skew insertion per Tx virtual lane, and user defined virtual lane to SerDes mapping for testing of the Rx PCS virtual lane re-order function

  5. PCS virtual lane statistics

    Relative virtual lane skew measurements (up to 2048 bits)
    Corrected Bit error, PreFEC BER

  6. FEC Total statistics

    Total corrected FEC symbols, Total uncorrected FEC symbols, Estimated Pre-FEC BER, Estimated Post-FEC BER, Pre-FEC Error Distribution Graph

  7. Link Flap

    Single short or repeatable link down events with ms precision

  8. Error Injection (PMA Layer)

    Repeatable error inject periods at PMA layer with ms precision

PHY/TRANSCEIVER ETHERNET TESTING

  1. Traffic generation

    Ethernet frames with FCS
    Traffic load: up to 100%
    Configurable Frame Size distribution and content
    Transmit and Receive Statistics

ADVANCED PHY FEATURES

  1. Equalization Controls

    Tx Transmit Equalization Controls

    • Pre-emphasis
    • Attenuation
    • Post-emphasis

    Optional Auto-Tune of Rx equalizer/CTLE

  2. Signal Integrity Analysis

    • FEC error correction chart
    • Advanced signal integrity view

HW SPECIFICATIONS

  1. Max. Power

    TBA

  2. Weight

    2.31 lbs (1.05 kg)

  3. Environmental

    Operating Temperature: 10 to 35º C
    Storage Temperature: -40 to 70º C
    Humidity: 8% to 90% non-condensing

  4. Regulatory

    FCC (US), CE (Europe)

  5. Notes

    This module is only supported by the Val-C12-2400 chassis
    This module requires two slots in the Val-C12-2400 chassis

Includes this free software

Technical Documentation

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